首页> 外文会议>IEEE Computer Society Annual Symposium on VLSI >Neural Networks as a Side-Channel Countermeasure: Challenges and Opportunities
【24h】

Neural Networks as a Side-Channel Countermeasure: Challenges and Opportunities

机译:神经网络作为侧频对策:挑战和机遇

获取原文

摘要

Specialized acceleration hardware for artificial deep neural network inference is available from the cloud to the edge. FPGAs in particular are heavily advertised for the acceleration of neural network-based applications. Traditionally, those applications are classification or nonlinear regression tasks with the goal to approximate an unknown function. However, they can be trained to replicate a fully known deterministic function - a classical example being the boolean XOR - as well. On the other hand, side-channel attacks remain a concern from the cloud to the edge, where attackers are often able to extract secret information through direct or indirect measurements of observables like power, voltage, electromagnetic emanation or timing. In this work, we show how an FPGA-mapped neural network implementation of the AES S-Box can improve side-channel resistance against Correlation Power Analysis (CPA) attacks. Although the implementation of a hardware-optimized algorithm such as the AES as a neural network introduces significant overhead, the generality of the representation allows to mitigate leakage in a manner agnostic to the overlying cryptographic primitive. We demonstrate the benefits of a generic representation, by optimizing an initially vulnerable neural network implementation towards side-channel resilience, through careful choice of activation function and input representation. The implementation is evaluated both against an external attacker measuring power with an oscilloscope, as well as a remote, internal adversary, who is able to capture voltage traces through FPGA-internal sensors in multi-tenant FPGAs. Our results show, how external attacks on the optimized neural network are no longer possible with up to one million traces, whereas an internal attacker is still able to recover the secret key. The latter result also exposes that in some cases measurement through internal sensors can be even more beneficial for an attacker than physical access with measurement equipment.
机译:用于人造深神经网络推理的专用加速硬件可从云到边缘。特别是FPGA尤为广告用于基于神经网络的应用程序的加速。传统上,这些应用程序是分类或非线性回归任务,其中目标是近似未知函数。但是,可以培训它们以复制完全已知的确定性函数 - 以及Boolean XOR的经典示例。另一方面,侧通道攻击仍然是云到边缘的担忧,其中攻击者通常能够通过电源,电压,电磁散发或定时等可观察到的可观察到的直接或间接测量来提取秘密信息。在这项工作中,我们展示了AES S盒的FPGA映射的神经网络实现如何改善对侧通道电阻的抗相关功率分析(CPA)攻击。虽然作为神经网络的硬件优化算法的实现引入了显着的开销,但是表示的一般性允许以覆盖密码原语不可知的方式减轻泄漏。我们通过仔细选择激活功能和输入表示,通过优化朝向信道弹性的最初易受攻击的神经网络实现,展示了通用表示的好处。该实现是针对具有示波器的外部攻击者测量功率以及远程内部对手,以及能够通过多租户FPGA中的FPGA内部传感器捕获电压迹线的遥控器。我们的结果表明,如何在最优化的神经网络上攻击不再可能具有高达100万次迹线,而内部攻击者仍然能够恢复密钥。后一种结果也暴露在某些情况下,通过内部传感器的测量可以比使用测量设备的物理访问更有用。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号