Recycled FPGA detection using exhaustive LUT path delay characterization

摘要

Field programmable gate arrays (FPGAs) have been extensively used because of their lower non-recurring engineering and design costs, instant availability and reduced visibility of failure, high performance and power benefits. Reports indicate that counterfeit FPGAs are infiltrating the IC supply chain, most of which are recycled type (previously used). Counterfeit components pose a significant threat to the government and industrial sectors of the economy because they undermine the security and reliability of the critical systems and networks. Recycled FPGA detection procedures include parametric test, functional test, and burn-in test that requires golden data and/or parts specifications from original component manufacturers. In this work, a sophisticated ring oscillator design method is used to exploit all the possible paths in look-up tables (LUTs). A recycled FPGA is likely to have fully used, partially used, and unused LUTs. The proposed mapping targets all paths of LUTs and forms a frequency array. A support vector machine is trained with frequency array from unused FPGAs, which differentiates between unused and aged FPGAs. An unsupervised method based on k-means clustering is also proposed to classify recycled components without golden information. Simulation and silicon results demonstrate high rates of success using the proposed methods.