A highly efficient external memory interface architecture for AVS HD video encoder

摘要

This paper presents a highly efficient external memory interface architecture to improve memory bandwidth utilization for AVS HD video encoder. Both burst and bank interleaved SDRAM accesses are intelligently adopted in the memory interface design. Our proposed architecture is composed of an address mapping layer and an arbitration layer. In the address mapping layer, according to the data request pattern and quantity, the clients in the encoder are divided into four groups which are assigned to different banks of the SDRAM. In each group, efficient address mapping schemes are proposed to minimize inner client overhead. In the arbitration layer, a straightforward group-based interleaved arbitration scheme is proposed to minimize inter client overhead. Experimental results show that the data access overhead cycles of our proposed interface design are reduced significantly and the bandwidth utilization is improved by up to 10% compared to the tile-linear address mapping scheme.