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FPGA implementation of moving object detection in frames by using background subtraction algorithm

机译:利用背景减法算法实现帧内运动目标检测的FPGA实现

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In this paper a new background subtraction algorithm was developed to detect moving objects from a stable system in which visual surveillance plays a major role. Among all existing algorithms it was choosen because of low computational complexity which is the major parameter of time in VLSI. The concept of the background subtraction is to subtract the current image with respect to the reference image and compare it with to the certain threshold values. Here we have written the core processor Microblaze is designed in VHDL (VHSIC hardware description language), implemented using XILINX ISE 8.1 Design suite the algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. The test results are seen to be satisfactory. The area taken and the speed of the algorithm are also evaluated.
机译:在本文中,开发了一种新的背景减法算法以从稳定的系统中检测移动物体,其中视觉监测发挥着重要作用。在所有现有的算法中,它是因为低计算复杂性而选择,这是VLSI中的时间的主要参数。背景减法的概念是相对于参考图像中的电流图像并将其与特定阈值进行比较。在这里,我们已经写了核心处理器微勃布设计在VHDL(VHSIC硬件描述语言)中设计,使用Xilinx ISE 8.1设计套件,通过与PC接口测试电路,在System C语言中写入算法并在Spartan-3 FPGA套件中进行测试使用RS232电缆。测试结果被认为是令人满意的。还评估所采用的区域和算法的速度。

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