A unique technique for reducing the effects of hot-carrier induced degradations in CMOS bistable circuits for fault tolerant VLSI design

摘要

The dominant degradation mechanisms in submicron CMOS devices have been identified as hot-carrier induced stress and may affect performance and reliability of VLSI circuits. The physical mechanisms responsible for the generation of the hot-carriers and its effects on device parameters must be clearly understood in order to model the degradation effects on circuit parameters forming part of the VLSI circuit. Using substrate current as a monitor and employing circuit level simulations over a typical operating cycle, the hot-carrier stress on MOS devices and its degradation effects have been modeled.