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A Compact E-Band PA with 22.37 PAE 14.29 dBm Output Power and 26 dB Power Gain with Efficiency Enhancement at Power Back-off

机译:紧凑型e频段PA,PAE 14.29 DBM输出功率和26 dB功率增益,电源效率提高

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This paper presents a compact power amplifier (PA) with efficiency enhancement technique at power back-off region in 65-nm CMOS technology for E-band applications. Cross-coupled transistor pair, generating negative impedance is introduced to enhance power back-off efficiency and small signal power gain. Neutralization and transformer-based matching networks are employed to improve gain and stability. The measured Psat, OP1dB and peak PAE are 14.29 dBm, 12.03 dBm and 22.37%, respectively. A 26 dB power gain with 3 dB bandwidth of 5 GHz is achieved. The measured peak gain varies from 26 dB to 31 dB and the P1dB power added efficiency increases from 6% to 13.3% by adjusting the control voltages of cross-coupled transistor pair. Compact layout of the PA yields a core area of 0.025 mm2, and the total DC power consumption is 120 mW, enabling compact and efficient integration into phased array transceivers.
机译:本文提出了一种紧凑的功率放大器(PA)与效率增强技术在功率回退区域在65纳米CMOS技术用于E-频带应用。引入交叉耦合晶体管对,以增强功率回效效率和小信号功率增益。采用中和和基于变压器的匹配网络来提高增益和稳定性。测量的p.<子的xmlns:MML = “http://www.w3.org/1998/Math/MathML” 的xmlns:的xlink = “http://www.w3.org/1999/xlink”>坐,op. 1db 峰值PAE分别为14.29 dBm,12.03 dBm和22.37%。实现了3个DB带宽为5 GHz的26 dB功率增益。测量的峰值增益从26 dB变化到31 dB和p 1db 通过调整交叉耦合晶体管对的控制电压,功率增加从6%增加到13.3%。 PA的紧凑型布局产生0.025毫米的芯面积 2 此外,总直流功耗为120 MW,使分阶段阵列收发器能够紧凑且有效地集成。

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