Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops

摘要

Dual edge-triggered flip-flop (DETFF) captures data at both clock edges. We observe that conventional sequential circuit that contains single edge-triggered flip-flops (SETFFs) can be simplified by identifying pairs of combinational subcircuits that are structurally identical, removing one subcircuit of each pair, and providing input data twice by using DETFFs where SETFFs have been used. The resulting circuit is named folded circuit. We carry the observation to technology mapping problem, so that many identical subcircuits are synthesized early on in the design process. Experimental results with some test circuits indicate that circuit area is reduced as much as 16%.