0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power 5T Cell

摘要

To achieve 0.5-V high-speed SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), combined with a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V_(DD)/2. The other is a partial activation of a multi-divided open-bit-line array without significant area penalty. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 5T-cell 4-kb array in a 128-kb SRAM core is able to achieve x6 faster and x14 lower power than the counterpart 6T-cell array, suggesting a possibility of a 540-ps cycle time at 0.5 V.