A 6supth/sup order, 700amp;#x2013;1100 MHz, 3.6 Gb/s RF bandpass amp;#x03A3;amp;#x0394; ADC with two-tone SFDR 67.2 dB in 65nm CMOS

摘要

This paper presents a 6th order, 700–1100 MHz, 3.6-Gb/s sampling continuous-time band-pass sigma-delta (CT BP ΣΔ) ADC realized in 65 nm CMOS technology. A high linearity transconductance-stage with Miller effect cancellation is proposed to provide above 30 dBm IIP3 over PVT corners. A 4-bit quantizer and non-return to zero (NRZ) feedback DACs are engaged in this design. The post-layout simulation shows a maximum 67.2 dB two-tone SFDR in 1-MHz bandwidth, IIP3 and noise figure are 4.3 dBm and 17.3 dB, respectively.