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A high speed VLSI architecture for scaled residue to binary conversion

机译:一种高速VLSI架构,用于缩放残留到二进制转换

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The scaled Chinese Remainder Theorem (CRT) is a very useful tool for the simplification of RNS to binary converters. The main drawback of this methodology is related to the use of large look-up tables that store the correspondence among the modular numbers and the corresponding scaled terms of the CRT. This fact limits the maximum speed allowed by this approach. In this paper a new method for the computation of the scaled factors is presented. It allows the computation of the scaled CRT output by using very small look-up tables implemented by conventional logic and simple and fast structures, that work in parallel. The only assumption made in order to develop the new algorithm is that the moduli must be odd.
机译:缩放的中文剩余定理(CRT)是一种非常有用的工具,用于简化到二进制转换器的RNS。该方法的主要缺点与使用存储在模块化数字之间的对应关系的大查找表和CRT的相应缩放术语的使用有关。这一事实限制了这种方法允许的最大速度。本文介绍了一种计算缩放因子的新方法。它允许通过使用由常规逻辑和简单和快速结构实现的非常小的查找表来计算缩放CRT输出,该表格并联工作。为了开发新算法而唯一的假设是模数必须是奇数。

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