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VLSI implementation of a low complexity 4#x00D7;4 MIMO sphere decoder with table enumeration

机译:具有表枚举的低复杂度4×4 MIMO球形解码器的VLSI实现

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In this work a sphere decoder with low complexity is proposed and implemented. We propose a simplified norm algorithm, which is called admissible set elimination (ASE), to dramatically decrease the number of searching nodes. In addition, the decoder uses table-look-up to acquire the enumeration order of different constellations. As a result, the critical path is shortened and the throughput is enhanced. Compared to the optimal ML detector, the proposed scheme greatly improves the complexity and throughput, while the performance only degrades around 0.5 dB. The proposed scheme is fabricated by a TSMC 90 nm process. The area is 0.85 mm2, and the average throughput can be up to 411.3 Mbps when the clock rate is 108.7 MHz.
机译:在这项工作中,提出并实现了一种具有低复杂度的球形解码器。我们提出一种简化的范数算法,称为可允许集消除(ASE),以显着减少搜索节点的数量。另外,解码器使用查表来获取不同星座的枚举顺序。结果,缩短了关键路径并提高了吞吐量。与最优ML检测器相比,该方案大大提高了复杂度和吞吐量,而性能仅下降了0.5 dB左右。所提出的方案是通过台积电90纳米工艺制造的。面积为0.85 mm 2 ,当时钟速率为108.7 MHz时,平均吞吐量可以达到411.3 Mbps。

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