HKMG all Last to Meet 20nm Logic Device Challenge

摘要

In this paper, we studied High-K & Metal Gate (HKMG) all last process for sub-28nm logic device, including gate insulator Tinv, gate leakage, hysteresis, device mobility, Gate Oxide Integrity (GOI) etc. We also evaluated the different interface layer of chemical oxide and conventional thermal oxide. Compared to the high-K first approach, the high-K last process can significantly improve gate insulator performance to meet the 20nm logic device requirements.