Using static voltage propagation approach to assist full chip LUP and TDDB physical verification

摘要

Latch-up (LUP) [1] and time-dependent dielectric breakdown (TDDB) [2] are well-studied reliability issues. For an individual technology node, LUP is often studied at the transistor/gate level, while interconnect TDDB [3] is often studied from breakdown model and metal-dielectric material composition point of view. However, the complexity of their effects on the function of circuit design during chip assembly is expanding beyond a single device/gate, residing deep inside a chip, and increasing with the advance of technology. Modeling their influence on layouts of larger circuits has proven very challenging; attempts to completely simulate a large design block or full chip with reliable outcomes have not been promising so far, due to the enormous amount of data to be processed and the input of uncertain simulation factors. It is critical for both foundries and independent device manufacturers (IDMs) to provide useful and feasible design guidelines for designers to follow to achieve successful tape-out. In this paper, we present a static voltage propagation approach and design automation methodology to assist and enhance rule-based LUP and TDDB design reliability verification in the chip assembly stage.