首页> 外文会议>China Semiconductor Technology International Conference >Study of Low Pinch-Off Voltage JFET in 500V High Voltage Process
【24h】

Study of Low Pinch-Off Voltage JFET in 500V High Voltage Process

机译:500V高压工艺中低夹紧电压JFET的研究

获取原文
获取外文期刊封面目录资料

摘要

This article presents a variety of small size JFET structures of low pinch-off voltage in 500V high voltage platform. The low pinch-off voltage is achieved by adopting low concentration channel area and implanting the opposite conductivity type impurity into the deep channel region, and the JFET current is improved by increasing the concentration of the part of channel region. Finally, the low pinch-off voltage and high current JFET device is achieved without mask adding.
机译:本文在500V高压平台中介绍了各种小尺寸JFET结构的低夹紧电压。通过采用低浓度通道区域并将相对的电导型杂质注入深通道区域,通过增加通道区域的浓度来实现低夹持电压。最后,在没有掩模添加的情况下实现了低捏 - 关闭电压和高电流JFET器件。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号