Closed form modelling for delay and slew metrics for on-chip VLSI RC interconnect for ramp inputs using F-distribution

摘要

Several approaches have been proposed for the accurate and efficient estimation of the on-chip interconnect delay and slew metrics. Moments of the impulse response are widely used for interconnect timing analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early phase design metrics or as design optimization cost functions. This paper describes a novel approach of fitting moments of the impulse response to probability density function, so that the interconnect delay and slew can be estimated accurately at an early physical design stage for both step and ramp input conditions. We have used Fisher-Snedecor distribution (F Distribution) to derive the delay and slew metrics for step as well as for ramp inputs. For RC trees it is demonstrated that the incomplete F function provides a probably stable approximation. The accuracy of our models is justified with the results obtained by using our approach, SPICE simulations and with that of the already established models. For calculations of both delay and slew, the relative error is less than 2 %.