45 nm-gate SOTB (Silicon on Thin BOX)) technology for LSTP application has been successfully developed. In the SOTB device, short-channel effect immunity without channel doping and back-gate bias threshold voltage (Vth) control are demonstrated. GIDL is reduced with avoiding drive current and inverter delay degradation minimum by optimizing offset source/drain extension to gate overlap. We have also proposed the SOTB device design enabling the controllable inverter delay and low Vth fluctuation for Logic and SRAM memory cell transistors. Inverter delay can be improved from 19.3 to 10.5 ps by applying the forward back-gate bias. Furthermore, Vth fluctuation can be reduced about 16% by applying the reverse back-gate bias. A 6-transistor SRAM memory cell of the SOTB structure by adding a reverse back bias control has shown to dramatically improve SRAM memory cell stability.
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