Stack effect implementation in OPC and mask verification forproduction environment

摘要

With the decrease of the transistors dimensions, process steps usually considered as not critical become challenging. Thisis the case for implant levels patterning, which can be strongly impacted by reflections from the underlying active andgate patterns, especially when no anti-reflective coating can be used. This stack effect leads to unexpected resist shape onwafer if not taken into account during OPC flow. We propose a solution to integrate stack effect onto existing OPCmodels by adding fictive layers at mask level in order to allow a stack-aware OPC or mask verification. This method canbe implemented in a standard OPC flow offered by EDA OPC software. It provides effective results compatible withproduction constrains, such as stack-aware full chip simulation and run time efficiency.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.