New Method of SOC Clock Design Based on Hierarchical Mode

摘要

The new problems of traditional clock design in hierarchical mode were analyzed in this paper and a new method of clock design was proposed. A phasesync signal was used as a bridge of top-level and sub-design in this method. It effectively prevents the 'damage' to the internal timing of sub-design caused by top-level timing closure. The application of this method avoids reset design of clock divider circuit and reduces the difficulty of physical design.