With the large data and complex problem of digital decimation filter for , the article designs a decimation filter using the comb filter and half-band filter cascade. To implement the comb filter in FPGA, using cascaded integrator form and reduce the bit width based Hogenaur cut off theory, implementing major components of half-band filter using pipeline technology combined with the internal structure of FPGA. Chip uses the Altera's cyclone series, occupying chip resources 1776 LE, with the speed of 19 MHZ.
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