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Design and Realization of Gigabit Ethernet Interface Based on FPGA

机译:基于FPGA的千兆以太网接口的设计与实现。

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Nowadays gigabit Ethernet is widely used in the area of computer and industry communication. In order to resolve the bandwidth of data transfer in high-speed data acquisition system, this paper introduces design principles and implementation methods of gigabit Ethernet interface based on FPGA. The physical layer hardware realization and the MAC layer realization are described in detail. At last, it presents the simulation through ISE simulator and validation on the hardware platform. The results show that the data transfer speed can reach lGbps and the design is very valuable in highspeed data acquisition system and software radio system.
机译:如今,千兆以太网已广泛用于计算机和工业通信领域。为了解决高速数据采集系统中数据传输的带宽问题,本文介绍了基于FPGA的千兆以太网接口的设计原理和实现方法。详细描述了物理层的硬件实现和MAC层的实现。最后,介绍了通过ISE仿真器进行的仿真以及在硬件平台上的验证。结果表明,数据传输速度可以达到1Gbps,该设计在高速数据采集系统和软件无线电系统中具有非常重要的价值。

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