High-Speed and Anti-Interference Parallel Bus Design on Board

摘要

This paper presents a high-speed and antiinterference parallel bus design on board, which takes a series of measures, including sourcesynchronous technology, the negative feedback technology, low-voltage differential transmission technology, error correction coding and pseudo-random code technology to improve the environment for parallel communication, increase communication speed, decrease error rate .The final test shows the communication speed has achieved 10 Gbps and the error rate has reduced to 10-7.