FPGA Implementation of Tierl Coding for JPEG2000

摘要

the tierl coding in JPEG2000 contains two coding blocks, the bit plane coding and arithmetic coding, which are all heavy computation and suitable for hardware implementation. The architectures for bit plane coding and arithmetic coding are designed and combined together to implement the tierl coding. The verilog HDL modules for tierl coding are programmed, simulated and synthesized to Altera's FPGA. The generated programming file is then downloaded to FPGA, the Altera's embedded logic analyzer, named Signal-Tap II, is used to debug the system, the result shows that the architectures designed in this paper are correct