Automatic Construction of Runtime Monitors for FPGA Based Designs

摘要

The failure of a hardware design may be catastrophic if there is a bug that exhibits during runtime. Such bugs may remain in the implementation due to shortfall in conventional testing and are referred to as corner case bugs. Runtime monitoring of hardware designs used in critical systems is required to take care of corner case bugs. The basic idea behind runtime monitoring is to identify certain critical design invariants and write assertions, which monitor these invariants during runtime. This paper describes a tool that translates properties written in PSL (Property Specification Language) into synthesizable VHDL called as monitors. These monitors can be synthesized along with the actual design. Automata theoretic approach is used for this translation.