Compact sub-milliwatt low-phase-noise CMOS LC-VCO based on power reduction technique

摘要

A power-minimized LC voltage controlled oscillator (VCO) with switched biasing and triode-region MOSFETs has been designed using a 0.18-µm CMOS process. The design strategy for an LC VCO suggested an inductance selection scheme to accommodate the trade-off between power consumption and phase noise. The VCO achieves a measured phase noise of −123.2 dBc/Hz at 1 MHz offset frequency. The Figure-Of-Merit with the normalized area of the proposed VCO is −198.2 dB.