Optimal coherent integration time design of 3^rd-order digital carrier tracking loop for weak signals in GNSS receivers

摘要

Conventional thermal noise phase jitter formula of GNSS receivers'' digital phase-locked loop (DPLL) for carrier recovery, which implies that the phase jitter monotonously decreases with the coherent integration time (CIT), can not be used for high-sensitivity DPLL design effectively. Variance comparison between I · Q phase detector (PD) which is normalized by the total power and two-quadrant arctangent PD indicates that the I · Q PD performs better than the other when used for tracking weak signals. The new thermal noise phase jitter formula for 3^rd-order carrier DPLL is derived based on the newly developed linear loop model. Analytical results show that there exists an optimal CIT for minimizing thermal noise phase jitter. Finally, the optimal CIT of 3^rd-order carrier DPLL is given by numerical method, which can be used for high-sensitivity digital carrier tracking loop design directly.