Design and FPGA implementation of modified Distributive Arithmetic based DWT-IDWT processor for image compression

摘要

Image compression is one of the major image processing techniques that is widely used in medical, automotive, consumer and military applications. Discrete wavelet transforms is the most popular transformation technique adopted for image compression. Complexity of DWT is always high due to large number of arithmetic operations. In this work a modified Distributive Arithmetic based DWT architecture is proposed and is implemented on FPGA. The modified approach consumes area of 6% on Virtex-II pro FPGA and operates at 134 MHz. The modified DA-DWT architecture has a latency of 44 clock cycles and a throughput of 4 clock cycles. This design is twice faster than the reference design and is thus suitable for applications that require high speed image processing algorithms.