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Computation-efficient FPGA implementation for flexible triangle search block-based motion estimation algorithm

机译:基于柔性三角形搜索块的运动估计算法的高效计算FPGA实现

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In this paper, a computation-efficient implementation of the flexible triangle (FTS) search algorithm is presented. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work. The FTS is used for block-based motion estimation where it can locate the best matching blocks between two frames using a search triangle of flexible size and orientation. This flexibility provide the triangle with the high efficiency to locate the best matching block in fewer number of search iterations. Further analyses of the FTS performance indicates that more computation efficiency can be achieved in loading the search area and the computing the matching criterion between two macroblocks. Adjacent search areas are overlapped and consequently, the loading mechanism can be modified to load only the non-overlapped sections In addition, loading of search area and other data can start earlier parallel with the algorithm initialization. Finally, the computed SAD results can be stored and then later used instead of re-computing them again. The proposed implementation in this paper reduces the average number of cycles required to finish one macroblock search by around 26% and thus enable the video encoder to support higher frequencies or larger resolutions. The proposed technique was implemented in FPGA as part of the flexible triangle search (FTS) motion estimation algorithm. The proposed design was implemented, simulated, and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the FTS algorithm published in previous work.
机译:本文介绍了柔性三角形(FTS)搜索算法的计算有效实现。 FTS是一种快速块匹配算法,用于在先前的工作中提出的运动估计。 FTS用于基于块的运动估计,其中它可以使用灵活尺寸和方向的搜索三角形定位两个帧之间的最佳匹配块。这种灵活性为三角形提供了高效率,以在更少数量的搜索迭代中找到最佳匹配块。进一步分析FTS性能指示在加载搜索区域和计算两个宏块之间的匹配标准时可以实现更多的计算效率。相邻的搜索区域是重叠的,因此,可以修改加载机制以仅加载非重叠部分,搜索区域和其他数据的加载可以与算法初始化一起开始。最后,可以存储计算的SAD结果,然后稍后使用而不是再次重新计算它们。本文提出的实施方式减少了完成一个宏块搜索所需的平均周期数约26%,从而使视频编码器能够支持更高的频率或更大的分辨率。该提出的技术在FPGA中实现,作为柔性三角形搜索(FTS)运动估计算法的一部分。使用VHDL实施,模拟和测试所提出的设计,并使用Xilinx ISE为Xilinx Spartan3装置合成。将获得的结果与先前工作中发布的FTS算法的FPGA实现进行比较。

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