A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder

摘要

In this paper, a ternary Full-Adder capable of reducing four input trits (ternary-digits) to two output trits is presented using the novel Ternary Adiabatic Logic (TAL) family. As well as presenting TAL, a possible design methodology for TAL circuits using Ordered Ternary Decision Diagrams (OTDDs) is presented, and the potential of higher-radix adiabatic logic families is discussed. Under typical process conditions on a 0.35µm process, front-end only simulations of the TAL Full-Adder using an ideal-ramp power-clock waveform show it to consume an average of 216fW per addition when operated at 1MHz.