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High density substrate solution for complex high pin count flip-chip applications

机译:适用于复杂的高引脚数倒装芯片应用的高密度基板解决方案

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There are a number of factors to consider when selecting an optimal semiconductor package configuration for the newer generations of high density controllers and processors; I/O requirement, package footprint, form factor, thermal dissipation, electrical performance, and cost. The more advanced microprocessor and ASIC semiconductor packaging currently require several thousand I/O contacts and they are expected to expand contact I/O by 30% in the very near future. This paper will detail the development of a unique raised contact substrate fabrication process that enables semiconductor developers to significantly reduce the contact pitch on the die without reducing pad size. The flip-chip to substrate assembly process yield is significantly higher as well because the conventional solder bumped die can be placed directly onto the raised contact features (eliminating the need for solder printing on the package substrate). Mounting the bumped die element on this planer topography solves fundamental issues associated with electro-migration and it avoids many of the current assembly process related defects. This is because the solid copper contact profile furnishes a consistent standoff height that enables a uniform and void free package interconnect as well as improving underfill flow control (even with low temperature solders).
机译:为新一代高密度控制器和处理器选择最佳的半导体封装配置时,需要考虑许多因素。 I / O要求,封装尺寸,外形尺寸,散热,电气性能和成本。目前,更先进的微处理器和ASIC半导体封装需要数千个I / O触点,并且有望在不久的将来将触点I / O扩展30%。本文将详细介绍独特的凸起式接触基板制造工艺的开发过程,该工艺可使半导体开发人员在不减小焊盘尺寸的情况下显着减小管芯上的接触间距。倒装芯片到基板的组装工艺良率也大大提高,这是因为可以将传统的焊料凸点管芯直接放置在凸起的接触部件上(从而消除了在封装基板上进行焊料印刷的需要)。将凸出的模具元件安装在该平面形貌上可以解决与电迁移相关的基本问题,并且可以避免许多当前与组装过程相关的缺陷。这是因为固态铜触点轮廓提供了一致的支座高度,该高度能够实现均匀且无空隙的封装互连,并改善了底部填充流量控制(即使使用低温焊料也是如此)。

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