CPU/FPGA-based real-time simulation of a two-terminal MMC-HVDC system

摘要

This paper presents a methodology for the CPU/FPGA-based real-time simulation of a two-terminal MMC-HVDC of up to 501 levels using a detailed equivalent model. The proposed modeling approach is validated using case studies of 101-levels and 501-levels MMC setups. Real-time simulation performance is demonstrated in singleand multi-rate simulation environments and under various operating conditions. Limitations to the approach are identified and discussed.