A new approach for FPGA-based real-time simulation of power electronic system with no simulation latency in subsystem partitioning

摘要

In real-time Hardware-in-the-Loop (HIL) test applications for power electronic systems, the main hurdle is to tackle with the mathematical models of variable topology of complex and high frequency driven converter. The most widespread solution is to separate the whole system into subsystems. However, partitioning method usually introduces simulation time step latency between different subsystems, which causes numeric instabilities especially when stiff situation occurs. In this paper, we propose a novel parallel simulation approach which has no time step latency in the whole system division, from which a numerically stable system modeling can be realized. Its numerical accuracy of the solution, the architecture design, and the issue pertaining to the parallel calculation are discussed in detail in this paper. The pertinence of the developed solution is also tested using a case study relating to a traction system power electronic application. For this case study, Implementations are made both on a 3 GHz Xeon CPU of RT LAB real-time simulator with a 2 mu s simulation step and a Field Programmable Gate Arrays (FPGA) Kintex-7 embedded in National Instruments FlexRIO PXIe-7975 enabling a simulation step below SO ns. Besides, comparison with results obtained from Simpower system in Matlab allows to evaluate the accuracy of our proposed modeling approach.