Charge recovery is a promising concept to design (cryptographic) VLSI circuits with low energy dissipation. However, unsatisfactory designs of proposed logic cells degrade its theoretical efficiency significantly both in its energy consumption and the resistance against differential power analysis attacks (DPA-attacks). Short circuit dissipation and non-adiabatic discharging of capacitance loads are the two major sources of this degradation which are addressed in this paper. In order to reduce these dissipation significantly, we manipulate threshold voltage of circuits transistors by body biasing. To evaluate the efficiency of our method we select a common charge recovery logic called 2N- 2N2P and examine it on 8-bit Brent-Kung adder as well as 4-bit, 8-bit and 16-bit 2N-2N2P carry look-ahead adders. Experimental results show at least 50% reduction in the energy consumption as compared to traditional 2N-2N2P. Moreover, using our technique reduces the dynamic power variation by a factor of 7.8 on the 2N- 2N2P inverter and therefore improves DPA-resistance of charge recovery circuits significantly.
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