We introduce probabilistic design, a methodology to design circuits using gates with probabilistic behavior. Probabilistic design is of great value, since the international technology roadmap for semiconductors (ITRS) forecasts that devices and interconnect are likely to suffer from frequent transient and permanent failures, as a consequence of technology scaling. We first provide the theoretical basis for probabilistic design, rooted in a novel Probabilistic Boolean Logic (pbl). By combining the properties of PBL with the properties of noise susceptible CMOS devices, we derive design principles and demonstrate that probabilistic design is a viable methodology to design circuits using gates with probabilistic behavior, which has been shown to be a useful approach for implementing ultra low-energy circuit designs.
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