Instruction scheduling is a crucial issue for cutting edge VLSI processors that exploit parallelism to solve the tradeoff between clock speed and power dissipation. A double scheme for multiple pipelines merges their scalar units into a multifunctional unit (MFU) and makes the MFU wave-pipeline. Parallelizing a resultant pipeline achieves instruction scheduling free due to multifunctionality. Applied such approach to the latest design of a ubiquitous processor, HCgorilla, this is implemented by using 0.18-ÿm CMOS standard cell chip.
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