Today, a great concern for the integration of high-frequency systems are the problems associated with the synchronization difficulties. The VCO block of PLLs is the primary source of timing jitter and this work addresses issues significant to the design of VCOs with Single-Ended Control in PLLs. The main goal of this work is to develop Two high frequency CMOS PLLs in 0.13μm technology. The advantage of a single-ended control line is the reduction of area and power. It is, on the other hand, very critical to examine the performance of a differential control in high performance PLLs.
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