PLLs generate clocks for the core logic in many ICs. As frequencies increase above 500 MHz, jitter and duty cycle error become significant and more likely to affect logic function. Measuring these parameters off-chip can be too expensive or impractical. This paper describes how a PLL BIST is being implemented in production ICs to test jitter, duty cycle, phase delay, frequency ratio, and lock time. It discusses some of the implementation problems and lessons, and how characterization was performed using a PC with graphical test generation software and off-the-shelf reference clock sources to produce production test patterns. Results for a test chip are included, demonstrating that calibrated, picosecond-precision measurements are now practical for production test.
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