In this paper, the problem of sizing an Operational Transconductance Amplifier (OTA) is addressed. The Pareto front is introduced as a useful analysis concept in order to explore the design space of such analog circuit. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the amplifier''s transconductance, slew rate, linear range and input capacitance are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, simulation results are presented, using a standard 0.5 μm CMOS technology.
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