A new fault generator suitable for reliability analysis of digital circuits

摘要

This paper deals with fault injection issues for reliability analysis. We propose a fault generator IP suitable for hardware emulation of single and multiple simultaneous faults occurence. The proposed IP is based on a very useful approach that allows the designer to control complexity and completness of the fault injection process. We provide models for cost and performance estimation of the IP. Also, synthesis results of its implementation on FPGA are given.