A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

摘要

The POWER7¿ microprocessor features a 32 kB L1 data cache with a 2R and banked-1W functionality using a 6T-SRAM cell. Read/write collision is intercepted inside the array with write-over-read priority. The array-specific power supply improves SRAM cell stability and performance while reducing the logic voltage level. The macro is fabricated in a 45nm CMOS SOI technology.