首页> 外文会议>IMECE2008;ASME international mechanical engineering congress and exposition >AUTOMATIC FEATURE RECOGNITION FOR DATA INTEROPERABILITY ISSUES IN HIGHSPEED ELECTRONICS SYSTEM DESIGN
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AUTOMATIC FEATURE RECOGNITION FOR DATA INTEROPERABILITY ISSUES IN HIGHSPEED ELECTRONICS SYSTEM DESIGN

机译:高速电子系统设计中数据互操作性问题的自动特征识别

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Technology trends toward higher speed and density devices have pushed high performance electronic system design to its limits. With fine miniaturization of very-large-scale integrated (VLSI) circuits and rapid increase in the working frequency of system-on-a-chip (SoC), the signal integrity has become a major concern. As the operating frequencies enter the gigahertz range, signal integrity issues such as cross talk, power-ground-plane voltage bounce, and substrate losses can no longer be neglected. In order to design high-performance electronic systems with fast time-to-market, it is often needed to analyze whole or part of the system at one fundamentally deeper level of physics. It has begun to be recognized that electromagnetic (EM) field analysis needs to be rigorously included as an addition to traditional circuit simulation. A common problem in this practice is the lack of efficient tools that enable engineers to easily transfer circuit board design data into EM solvers. To partially solve this problem, ACIS SAT has been introduced as a standard data exchange format and been adopted by many software vendors for data import and export. However, efficient data transfer remains a problem as the geometry created in the design package becomes static and no longer feature-based once imported into the simulation package. In this paper,automatic feature recognition algorithms are implemented to help extract features and parameters from the imported static model in SAT format. Case studies will be provided for some representative high speed electronics designs. This work is supported by Research & Technology Development Grant Program of Washington Technology Center with a goal to achieve improved design process for high-speed electronic systems. The developed tool has a potential to speed up the current design process by eliminating laborious manual preparation of design data for EM simulation and allow what-if analysis to be automated to highlight likely signal integrity issues.
机译:朝着更高速度和密度的设备发展的技术趋势已将高性能电子系统设计推向了极限。随着超大规模集成电路(VLSI)的精细小型化以及片上系统(SoC)的工作频率的迅速增加,信号完整性已成为主要关注的问题。随着工作频率进入千兆赫范围,信号完整性问题,例如串扰,电源接地平面电压反弹和基板损耗将不再被忽略。为了设计出具有快速上市时间的高性能电子系统,通常需要从根本上更深层次的物理学角度来分析整个系统或部分系统。已经开始认识到,除了传统的电路仿真之外,还必须严格包括电磁场(EM)分析。这种实践中的一个普遍问题是缺乏有效的工具,使工程师无法轻松地将电路板设计数据传输到EM解算器中。为了部分解决此问题,已将ACIS SAT作为一种标准的数据交换格式引入,并被许多软件供应商所采用以进行数据导入和导出。但是,有效的数据传输仍然是一个问题,因为在设计包中创建的几何形状变为静态,并且一旦导入到仿真包中便不再基于特征。在本文中, 实现了自动特征识别算法,以帮助从SAT格式的导入的静态模型中提取特征和参数。将为一些代表性的高速电子设计提供案例研究。这项工作得到华盛顿技术中心的研究与技术开发资助计划的支持,目的是实现改进的高速电子系统设计流程。开发的工具有可能通过消除费力的手动准备用于EM仿真的设计数据来加快当前的设计过程,并使假设分析自动进行以突出可能的信号完整性问题。

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