Automatic clock jitter analysis considering clock divider

摘要

Clock jitter can cause degradation in the system performance. New and efficient clock jitter analysis methodology is presented in this paper. Odd-number clock divider as well as even-number clock divider can be automatically taken into consideration during clock jitter analysis. Furthermore, worst case clock jitter analysis is possible since the state dependency is also considered. This methodology has been compared with the measured data of silicon. Even though monitoring points of simulation and measurement are different, the accuracy of simulation is within 20% compared to the measurement data.