Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory

摘要

Multimedia applications are characterized by a largenumber of data accesses and complex array index manipulations.The built-in address decoder in the RAM memorymodel commonly used by most memory synthesis tools, unnecessarilyrestricts the freedom of address generator synthesis.Therefore a memory model in which the address decoderis decoupled from the memory cell array is proposed.In order to demonstrate the benefits and limitations of thisalternative memory model, synthesis results for a Shift Registerbased Address Generator that does not require addressdecoding are compared to those for a counter-basedaddress generator that requires address decoding. Resultsshow that delay can be nearly halved at the expense of increasedarea.