Microprocessors are today getting more and moreinefficient for a growing range of applications. Itsprinciples -The Von Neumann paradigm[3]- based on thesequential execution of algorithms will no longer be ableto cope with the kind of highly computing intensiveapplications of multimedia world.Nowadays approaches to deal with these limitationsconsist in the following:- The first, and most natural way to increase thecomputing power is obviously to decrease the cycleexecution time, thanks to new silicon technology: Thefunctional frequencies for the newcomers CPUs are nowgetting on the way to 2 GHz.- The second approach is co-design. The intended generalpurpose CPU will confide the computation of the mosttime demanding applications to a dedicated core. Themost famous example are PC graphic cards whichmanage all the 2D and 3D display operations that evenhigh-end CPUs are not able to handle efficiently.Both methods are not satisfying. The first one quicklyfinds its limitations in however limited functionalfrequencies and power consumption reduction, as thesecond requires the design of a new core for eachintended algorithm. New parallel execution basedmachine paradigms must be considered. Thanks to theirhigh level of flexibility structurally programmablearchitectures are potentially interesting candidates toovercome classical CPUs limitations.Based on a parallel execution model, we present in thispaper a new dynamically reconfigurable architecture,dedicated to data oriented applications acceleration.Principles, realizations and comparative results will beexposed for some classical applications, targeted ondifferent architectures.
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