Injection-Locked Clocking: A New GHz Clock Distribution Scheme

摘要

We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injection-locked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18mum digital CMOS technology. It has four divide-by-2 ILOs at the leaves of a 3-section H-tree, generating 5GHz local clocks from the 10GHz input clock with 17% locking range and no phase noise degradation. Measured jitter of generated clocks is lower than that of the input signal. Two local clocks can be differentially deskewed up to 80ps relative to each other. The test chip consumes only 7.3mW excluding test-port buffers