Multiple-valued mask-programmable logic array using one-transistoruniversal-literal circuits

摘要

This paper presents a compact multiple-valued mask-programmablelogic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-levelsynthesis. A universal literal in the MIN plane is decomposed into athreshold literal and a logic-value conversion (LVC) that is shared inthe same column of the MIN plane. Since a threshold literal can bedesigned by using a single floating-gate MOS transistor, a compact MINplane can be implemented in the proposed MPLA. Any arbitraryuniversal-literal circuits can be realized by programming the thresholdvoltage of the corresponding floating-gate MOS transistor and selectingan appropriate LVC as an input variable. The performance of the proposedMPLA is evaluated under a 0.8 μm CMOS design. It is demonstrated thatits performance is superior to that of conventional PLA's