首页> 外文会议>Electronic Components and Technology Conference, 2005. Proceedings. 55th >Premolded copper leadframe substrate: an enabling technology for advanced unmolded substrate packages
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Premolded copper leadframe substrate: an enabling technology for advanced unmolded substrate packages

机译:预成型的铜引线框架基板:先进的未成型基板封装的使能技术

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The trend of package miniaturization in the field of electronics is a key driver towards development of novel packages with superior electrical & thermal performances. Several power package designs use the solder bumping technology to improve RDSon & thermal resistance. These include the MOSFET BGA [Granada et al., 2003] and Flip Chip in a Leaded Molded Package [Joshi et al., 2004] (FLMP). Both packages attained low electrical and thermal resistances by providing short and unrestricted routes of the drain, source & gate contacts towards the package external, hence, towards the printed circuit board (PCB). The MOSFET BGA for example have direct source and gate contacts to the PCB through die solder bumps, while drain contacts are maximized through the use of leadframe substrate with peripheral protrusions or solder balls coplanar to the source bumps which are directly soldered to the board. The FLMP on the other hand is designed to have the die backside (drain contact of the MOSFET) soldered directly to the board while the source & gate contacts (leads of the package) are formed coplanar to the die backside. Both MOSFET BGA & FLMP are electrically & thermally versatile relative to its size. A new packaging idea has emerged by combining the best features of these two packages. This new package is called MaxFET. It is an unmolded substrate package, which adopts the FLMP direct soldering concept of die backside to the PCB, hence maximizing the drain connection. Source path of the package to the PCB is shortened by using leadframe substrate and ball attach technology such as that of the MOSFET BGA. The substrate is the main external framework of MaxFET package, thus electrical, thermal, mechanical and size considerations are significant factors in the design. Development of ultra-thin premolded leadframe substrate for MaxFET packaging will be detailed and discussed along with finite element analysis and preliminary reliability testing.
机译:电子领域封装小型化的趋势是开发具有卓越电气和热性能的新型封装的关键驱动力。几种电源封装设计使用焊料凸点技术来改善RDSon和热阻。这些包括MOSFET BGA [Granada等,2003]和引线模制封装中的倒装芯片[Joshi等,2004](FLMP)。两种封装均通过提供短,无限制的漏极,源极和栅极接触点朝着封装外部,因此朝着印刷电路板(PCB)的路径,实现了低电阻和热阻。例如,MOSFET BGA通过芯片焊点与PCB形成直接的源极和栅极接触,而漏极接触则通过使用具有与源极凸点共面的外围凸起或焊球的引线框基板来实现,源极凸点直接焊接到板上。另一方面,FLMP旨在将管芯背面(MOSFET的漏极触点)直接焊接到板上,同时将源极和栅极触点(封装的引线)形成为与管芯背面共面。 MOSFET BGA和FLMP相对于其尺寸在电气和热方面都是通用的。通过结合这两种包装的最佳功能,出现了一个新的包装理念。这种新封装称为MaxFET。它是未模压的基板封装,采用管芯背面到PCB的FLMP直接焊接概念,从而最大限度地提高了漏极连接。通过使用引线框基板和球形附着技术(例如MOSFET BGA),缩短了封装到PCB的源极路径。基板是MaxFET封装的主要外部框架,因此电气,热,机械和尺寸方面的考虑是设计中的重要因素。将对用于MaxFET封装的超薄预成型引线框架基板的开发以及有限元分析和初步的可靠性测试进行详细讨论。

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