Integration of multi-level copper metallization into a highperformance sub-0.25 μm CMOS technology

摘要

A high performance sub-0.25 μm CMOS technology has beendeveloped with six levels of planarized copper interconnects. 0.15 μmtransistors (L_gate=0.15 μm) are optimized for 1.8 Voperation to provide high performance with low power-delay products andexcellent reliability. Copper has been integrated into the back-end toprovide low resistance interconnects to minimize wiring induced RCdelays