For devices operating mainly in the standby or low power mode, energy saving from dynamic voltage scaling (DVS) is limited due to very poor efficiency of the PWM DC/DC converter operating at light load conditions, resulting in shorter than expected battery life. This paper first presents the design of a DVS controller - realized on a Xilinx CoolRunner 2 CPLD - having a 25μs worst case transient response and 15 mV average Vddstep size across an 1.30-1.90 V range. Next a scheme is proposed in which the DVS controller automatically selects between the PFM and PWM mode DC/DC conversion to realize maximum power saving across full range of load conditions.
展开▼