In current VLSI circuits, there can be hundreds of required I/O pins. BGA(Ball Grid Array) packaging is commonly used to realize the huge number of connections between VLSI and PCB. In this paper, we propose a global routing method for two-layer BGA packages. In our routing model, the global routing for each net is uniquely determined by a via assignment. Our global routing method begins with an initial feasible via assignment and incrementally improves the via assignment to minimize the total wire length and wire congestion. In each iteration, a via assignment is improved by exchanging adjacent two vias, rotating three vias, or by moving vias to their adjacent grids one by one. Our method is a greedy-based heuristic. The algorithm efficiently generates better global routes than initial routes with respect to wire congestion and total wire length.
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