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Manufacturing-aware Design Methodologies for Mixed-Signal Communication Circuits

机译:混合信号通信电路的制造感知设计方法

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Mixed-signal communication circuits are becoming a very common component of systems-on-a-chip as part of modern communication systems. The implementation of DFM and DFT methodologies is critical to enhance communication across the tape-out barrier critical for these circuits. We present a manufacturing-aware design methodology specifically targeting integrated communication circuits in systems-on-a-chip (SoC). The key principle behind the methodology is that flexible design methods which can effectively adjust a design's power consumption and functionality to its application can also provide critical reductions in manufacturing-induced design risk. The methodology is based on the following four techniques: goal-based design that directly relates top level goals with low level manufacturing-dependent parameters; semi-custom voltage-island physical design techniques; adaptive architecture design; and intelligent on-line at-speed monitoring and problem determination techniques. We describe these four methodology features, and illustrate them on a multi-protocol CMOS 3.2 Gbits/second low-power serial communications core. The presented data shows how this methodology results in better and more cost-effective adaptability of the design to manufacturing and post-manufacturing conditions, thereby improving turnaround time, yield, and overall profit.
机译:作为现代通信系统的一部分,混合信号通信电路正成为片上系统的非常常见的组件。 DFM和DFT方法的实现对于增强跨越这些电路至关重要的流片屏障的通信至关重要。我们提出了一种制造感知设计方法,专门针对片上系统(SoC)中的集成通信电路。该方法背后的关键原理是灵活的设计方法,可以有效地调整设计的功耗和功能以适应其应用,还可以显着降低制造引起的设计风险。该方法基于以下四种技术:基于目标的设计,直接将顶级目标与低级别的制造相关参数相关联;半定制的电压岛物理设计技术;自适应架构设计;以及智能的在线实时监控和问题确定技术。我们描述了这四种方法的功能,并在多协议CMOS 3.2 Gbit / s低功耗串行通信内核上进行了说明。呈现的数据显示了这种方法如何使设计对制造条件和制造后条件具有更好,更具成本效益的适应性,从而改善了周转时间,良率和总体利润。

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